
scren1 equ $b000
scren2 equ $e000
buf equ scren1
src equ $2000

sr equ $80
bf equ sr+2
frm equ bf+2
clock equ frm+1
col equ clock+1

 org src
 ins 'fade.ani'

 org $400
main
 lda >scren1
 eor >scren2
 sta e1+1
 sta e2+1

 ldx <ant
 ldy >ant
 stx 560
 sty 561
 lda #%00100011
 sta 559
 lda #15
 sta 708

 lda 20
 cmp 20
 beq *-2

 sei
 lda #$fe
 sta $d301
 lda #0
 sta $d40e

 ldx #32
 ldy #0
 tya
cl1 sta scren1-$10,y
cl2 sta scren2-$10,y
 dey
 bne cl1
 inc cl1+2
 inc cl2+2
 dex
 bne cl1

 ldx <nmi
 ldy >nmi
 stx $fffa
 sty $fffa+1
 lda #$17   ;pierwsze opuznienie
 sta clock

 lda #$40
 sta $d40e

go lda src+4 ;liczba klatek
 sta frm
 asl @
 clc
 adc #10
 adc frm
 clc
 adc <src
 sta sr
 lda #0
 adc >src
 sta sr+1

 ldy #0
anm lda #1
 beq anm
 lda #0
 sta anm+1

 jsr depack

 ldy frm
 dey
 tya
 lsr @
 lsr @
 sta kol+1

 ldy #2
 dec frm
 bne anm
 jmp go

* Depacker

depack equ *
mad lda <buf
 sta bf
sad lda >buf
 sta bf+1

 tya
 clc
 adc sr
 sta sr
 bcc *+4
 inc sr+1

dep ldy #0
 lda (sr),y
 tax
 and #$c0
 beq unp2
 cmp #$40
 beq rle
 cmp #$c0
 beq imp

unp1 inc sr
 bne *+4
 inc sr+1
 txa
 and #$3f
 tax
u1 lda (sr),y
 sta (bf),y
 iny
 dex
 bpl u1
 tya
 clc
 adc bf
 sta bf
 bcc *+4
 inc bf+1

 tya
 clc
 adc sr
 sta sr
 bcc *+4
 inc sr+1
 jmp dep

exit rts
unp2 txa
 iny
 ora (sr),y
 beq exit
 lda (sr),y
 clc
 adc bf
 sta bf
 txa
 adc bf+1
 sta bf+1
 lda #2
 clc
 adc sr
 sta sr
 bcc *+4
 inc sr+1
 jmp dep

rle txa
 and #$3f
 tax
 inc sr
 bne *+4
 inc sr+1
 lda (sr),y
r sta (bf),y
 iny
 dex
 bpl r
 tya
 clc
 adc bf
 sta bf
 bcc *+4
 inc bf+1

 inc sr
 bne *+4
 inc sr+1
 jmp dep

imp txa
 and #$3f
 tax
 iny
 lda bf
 sec
 sbc (sr),y
 sta i+1
 iny
 lda bf+1
 sbc (sr),y
 sta i+2

 ldy #0
i lda $ffff,y
 sta (bf),y
 iny
 dex
 bpl i
 tya
 clc
 adc bf
 sta bf
 bcc *+4
 inc bf+1

 lda #3
 clc
 adc sr
 sta sr
 bcc *+4
 inc sr+1
 jmp dep

nmi pha
 tya
 pha
 sta $d40f

kol lda #0
 sta $d016

 inc 20

 dec clock
 bne skp

 lda adr+1
e1 eor #0
 sta adr+1
 lda sad+1
e2 eor #0
 sta sad+1

delay ldy #0
 lda src+10,y  ;opoznienie w ramkach
 sta clock
 sta anm+1
 inc delay+1
 lda delay+1
 cmp src+4
 bne skp
 lda #0
 sta delay+1

skp pla
 tay
 pla
 rti

ant dta b($4b)
adr dta a(scren2)
 dta d'++++++++++++++++++++'
 dta d'++++++++++++++++++++'
 dta d'++++++++++++++++++++'
 dta d'++++++++++++++++++++'
 dta d'++++++++++++++++++++'
 dta d'++++++++++++++++++'
 dta b($41),a(ant)

 run main